The present invention generally relates to a semiconductor memory device having a charge barrier layer and a method for producing the same, and more particularly, to improvements in the charge barrier layer.
Recently, there has been considerable activity in the development of a dynamic random access memory (DRAM) device having an increased integration density. It is required particularly to reduce the size of an area of a memory cell which occupies a semiconductor chip. Therefore, there is a tendency for a memory capacitor to be reduced.
It is known that .alpha.-particles-induced soft errors increase with a decrease in size of the memory capacitor. Soft errors refer to a random failure not related to a physically defective device. When .alpha.-particles entires the semiconductor substrate, electron-hole pairs are generated. Holes move toward an electrode on the semiconductor substrate. On the other hand, electrons are diffused while some electrons are recombined with holes, and are collected in a depletion region under a gate electrode, a source region or a drain region. Further, electrons are collected in the source or drain region. The electrons captured in the depletion region or the source or drain region cause an erroneous operation of DRAM devices. The influence of .alpha.-particles is also a problem in a static random access memory device (SRAM device).
In order to suppress the occurrence of soft errors, various proposals have been reported. A proposal teaches an increase of the impurity concentration in a silicon semiconductor substrate. Another proposal teaches a p.sup.+ -type impurity diffusion region formed in a semiconductor substrate so as to be positioned below n.sup.+ -type diffusion regions such as source and drain regions formed in the semiconductor substrate. The p.sup.+ -type impurity diffusion region functions as a charge barrier layer for preventing electrons arising from the movement of .alpha.-particles in the semiconductor substrate, from being collected in the depletion regions, and source and drain regions. The p.sup.+ -type charge barrier layer is described in the Japanese Laid-Open Patent Application No. 58-107667, which corresponds to the U.S. patent application Ser. No. 333,230, now U.S. Pat. No. 4,506.436.
However, the prior art disclosed in the above paper has disadvantages as follows. The charge barrier layer is formed at the same depth from various points on the main surface of the substrate. Therefore, a vertical width of a depletion region formed under the impurity diffusion region such as source and drain regions is not identical to a vertical width of a depletion region of a channel under the gate electrode located between the source and drain regions. As a result, a portion of the charge barrier layer with respect to the depletion regions formed under the source and drain regions is different in charge collecting ability from a portion of the charge barrier layer with respect to the depletion region under the gate electrode. Normally, the charge barrier layer is formed at an optimum depth determined based on a vertical width of the depletion region under the source or drain region. In this case, since the depletion region under the gate electrode is unnecessarily wide in the vertical (depth) direction of the substrate, the p.sup.+ -type diffusion region cannot provide a sufficient function of preventing charges (electrons) due to .alpha.-particles from being collected in the depletion region under the gate electrode and the source and drain regions. It is noted that an increased vertical width of the depletion region has the increased ability of capturing electrons due to .alpha.-particles. Further, in the above case, the charge barrier layer hardly functions with respect to electrons generated due to oblique incidence of .alpha.-particles. On the other hand, if the charge barrier layer is formed at an optimum depth determined based on a vertical width of the depletion region under the gate electrode, the vertical width of the depletion region under the source or drain region exceeds a peak of an impurity concentration of the p.sup.+ -type charge barrier layer.